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  • 2017年度の研究業績



  • J.An, M. Namai, H. Yano, and N.Iwamuro, “Investigation of Robustness Capability of -730 V P-Channel Vertical SiC Power MOSFET for Complementary Inverter Applications,” IEEE Trans. Electron Devices, Vol. 64, No.10, pp:4219-4225, Oct. 2017, doi: 10.1109/TED.2017.2742542.
  • Tetsuo Hatakeyama, Yuji Kiuchi, Mitsuru Sometani, Shinsuke Harada, Dai Okamoto, Hiroshi Yano, Yoshiyuki Yonezawa, and Hajime Okumura, “Characterization of traps at nitrided SiO2/SiC interfaces near the conduction band edge by using Hall effect measurements,” Applied Physics Express, vol. 10, p.046601, 2017.
  • Haruka Shimizu, Akio Shima, Yasuhiro Shimamoto, and Noriyuki Iwamuro,”Ohmic contact on n- and p-type ion-implanted 4H-SiC with low-temperature metallization process for SiC MOSFETs,” Japanese Journal of Applied Physics, vol.56, Issue 4S, 04CR15, (2017)
  • A. Niwa, T. Imazawa, R. Kojima, M. Yamamoto, T. Sasaya, I. Takanori, H. Tadano, “A Dead Time Controlled Gate Driver Using Current Sense FET Integrated in SiC MOSFET,” IEEE Trans. on Power Electronics (2017) DOI:10.1109/TPEL.2017.2704620
  • M. Okamoto, M. Sometani, S. Harada, H. Yano, and H. Okumura, “Dynamic Characterization of the Threshold Voltage Instability under the Pulsed Gate Bias Stress in 4H-SiC MOSFET”, Mater. Sci. Forum, Vol. 897, pp.549-552 (2017).  DOI: 10.4028/www.scientific.net/MSF.897.549
  • X. Zhang, D. Okamoto, T. Hatakeyama, M. Sometani, S. Harada, R. Kosugi, N. Iwamuro, H. Yano, “Characterization of near-interface traps at 4H-SiC metal-oxide-semiconductor interfaces using modified distributed circuit model,” Appl. Phys. Express (2017) DOI:10.7567/APEX.10.064101


  • T.Goto, T.Shirai, A.Tokuchi, T.Naito, K.Fukuda, and N.Iwamuro, “Experimental demonstration on ultra-high voltahe and high speed 4H-SiC DSRD with smaller numbers of die stacks for pulse power applications,” Abstract of ICSCRM2017, September, 2017,Washington D.C, MO.D1.2.
  • Masaki Namai, Junjie An, Hiroshi Yano and Noriyuki Iwamuro, “Experimental and Numerical Demonstration and Optimized Methods for SiC Trench MOSFET Short-Circuit Capability,” in Proceedings of International Symposium on Power Semiconductor Devices & ICs (ISPSD)2017, pp.363-366, (2017).
  • Rene Barrera-Cardenas, Jiantao Zhang, Takanori Isobe, Hiroshi Tadano, “Influence of CCM and DCM Operation on Converter Efficieny and Power Density of a Single-Phase Grid-Tied Inverter” in Proceedings of International Future Energy Electronics Conference 2017 (IFEEC 2017), June 3-7 2017, Kaohsiung, Taiwan.
  • Zijin He, Long Zhang, Takanori Isobe, Hiroshi Tadano, “Dynamic Performance Improvement of Single-Phase STATCOM with Drastically Reduced Capacitance” in Proceedings of International Future Energy Electronics Conference 2017 (IFEEC 2017), June 3-7 2017, Kaohsiung, Taiwan.


  • 髙橋勇紀, 飯嶋竜司, 磯部高範, 只野博, 山﨑長治, 長谷川智宏, “スイッチ型クライストロンモジュレータへの出力電圧補償回路の適用に関する検討”,  日本加速器学会 第14回年会, 札幌市(北海道大学 札幌キャンパス), 2017年8月1日~8月3日
  • 唐本祐樹, 張旭芳, 岡本大, 染谷満, 畠山哲夫, 原田信介, 岩室憲幸, 矢野裕司, “コンダクタンス法によるp型SiC MOSキャパシタ界面特性の解析”, 第78回応用物理学会秋季学術講演会, 福岡国際会議場, 2017年9月5日~8日
  • 張旭芳, 岡本大, 畠山哲夫, 染谷満, 原田信介, 岩室憲幸, 矢野裕司, ”Verification of density distribution of near-interface traps in 4H-SiC MOS capacitors with different oxide thicknesses,”第78回応用物理学会秋季学術講演会, 福岡国際会議場, 2017年9月5日~8日


  • Noriyuki Iwamuro, “Power Semiconductors Shape up for Future Vehicles”, ASIA ELECTRONICS INDUSTRY, 2017年6月号 電波新聞社
  • Junjie An, Masaki namai, Mikiko Tanabe, Dai Okamoto, Hiroshi Yano, and Noriyuki Iwamuro, “Making a debut: the p-type SiC MOSFET”, Compound Semiconductor, June, 2017.


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